`timescale 1ns / 10ps
`define clock_period 20

module counter8_tb;

	reg cin, clk, load;
	reg[7:0] data;
	wire cout;
	wire[7:0] out;
	
	counter8 cnt0(
		.out(out),
		.cout(cout),
		.data(data),
		.load(load),
		.cin(cin),
		.clk(clk)
	);

	always #(`clock_period / 2) clk = ~clk;
	
	initial begin

		data = 8'b0000_0000;
		clk = 1'b0;
		cin = 1'b0;
		load = 1'b0;
		#(`clock_period)
		load = 1'b1;
		#(`clock_period)
		load = 1'b0;
		#(`clock_period * 16)
		//同步置数为8'b1010_1010
		data = 8'b1010_1010;
		load = 1'b1;
		#(`clock_period)
		load = 1'b0;
		#(`clock_period * 16)
		//同步置数为8'b1111_1111,cin = 1时的情况
		cin = 1'b1;
		data = 8'b1111_1111;
		load = 1'b1;
		#(`clock_period)
		load = 1'b0;
		cin = 1'b0;
		#(`clock_period * 16)
		
		$stop;
	end
	
endmodule
